Traditionally, package wiring substrates that are configured to have high density by means of a multilayer structure have been in demand. In that regard, as a wiring substrate configured to have a multilayer and high-density structure, a buildup substrate is known that includes interstitial vias (IVHs) formed in a core layer for establishing an electrical connection between specific layers, IVH pads formed on the core layer, vias formed in a buildup layer, via pads formed on the buildup layer, and wiring patterns. Such a multilayer buildup substrate is also known to function as a package substrate unit.
Explained below with reference to FIG. 19 is an exemplary configuration of a conventional package substrate unit 100 having a multilayer structure. Herein, FIG. 19 is a configuration diagram of the conventional package substrate unit 100. FIG. 20A is a cross-sectional view of a conventional semiconductor chip mounting layer. FIG. 20B is a plan view of the conventional semiconductor chip mounting layer.
As illustrated in FIG. 19, the package substrate unit 100 includes a semiconductor chip mounting layer 3, a ball grid array (BGA) solder ball mounting layer 19, an insulation layer 4 (FIG. 20A), and an insulation layer 5. Besides, it is formed to have a multilayer buildup structure that includes insulation layers 14 functioning as topside and underside buildup layers respectively and each having vias 12 and via pads 13, a core layer 15, and solder resist layers 7 and 16.
In the core layer 15, through holes 17 are formed at predetermined positions. In each through hole 17 is placed a through hole via 18 with a pair of the via pads 13 lying above and below. Besides, in the package substrate unit 100, a semiconductor chip 10 is mounted as an electronic component on the top surface of the semiconductor chip mounting layer 3.
The semiconductor chip mounting layer 3 includes the insulation layer 4 (FIG. 20A), conductive pads 6 and the solder resist layer 7 that are formed on the top surface of the insulation layer 4. On the solder resist layer 7, openings 8 that are located at the upper side are formed at predetermined positions (FIG. 19). Solder bumps 11 that are formed at the end terminals of the semiconductor chip 10 form solder joints with solder bumps 9 that are formed at the openings 8, which are formed on the solder resist layer 7 of the semiconductor chip mounting layer 3. Herein, eutectic solder (Sn/Pb) is used in the solder bumps 9.
Meanwhile, in a publication that discloses a conventional technology, a package substrate has been disclosed in which copper posts and copper bumps functioning as electroplating electrodes for forming solder joints with the copper posts are provided in solder bumps that are formed on a base resin layer on which an electronic component such as a semiconductor chip is mounted.
Patent Literature 1: Japanese Laid-open Patent Publication No. 2008-42118
In recent years, from the perspective of environmental measures, there has been a shift from eutectic solders (Sn/Pb) to lead-free solders not containing lead (Pb) (for example, Sn/Ag, Sn/Ag/Cu, Sn/Cu, etc.) as the solders used at the time of mounting semiconductor chips.
Here, lead-free solders have a higher melting-point temperature (for example, 220° C.) than the melting-point temperature (for example, 183° C.) of eutectic solders. Hence, the difference in thermal expansion at the time of mounting the semiconductor chip 10 in the package substrate unit 100 (i.e., during the reflow process) causes lead-free solders to be prone to strain. Besides, since the lead-free solders have a higher degree of hardness than eutectic solders, the lead-free solders are more prone to cracks than the eutectic solders.
Explained below with reference to FIGS. 20A and 20B are the factors causing cracks in the solder bumps 9 if lead-free solders are used. Herein, the stress on each solder bump 9 is generated at the interfaces between different materials. More particularly, the stress occurs at the interfaces (indicated by black circles α in the figure) between the solder bumps 9 and the respective openings 8 on the solder resist layer 7 and occurs at the interfaces (indicated by black circles β in the figure) between the conductive pads 6 and the respective solder bumps 9.
Particularly, since the stress gets concentrated at the interfaces between the solder bumps 9 and the respective openings 8 on the solder resist layer 7, cracks occur from the interfaces (indicated by black circles a in the figure) between the solder bumps 9 and the respective openings 8 on the solder resist layer 7 toward the central portion of the solder bumps 9. When such cracks occurs inside the solder bumps 9, it effects the connection strength between the solder bumps 9 and the respective solder bumps 11, which are formed at the end terminals of the semiconductor chip 10 (FIG. 19).
Meanwhile, in the case of the package substrate disclosed in the conventional technology publication, since the copper posts are formed in the through hole of a base resin layer, the substrate cannot be configured to be a high density substrate. Moreover, in order to form the copper bumps that form solder joints with the copper posts, it is necessary to perform the task of forming openings in the base resin layer by using an expensive laser machine. Besides, it is also necessary to perform the task of uniting or aligning the base resin layer having the copper posts formed thereon with a substrate having solders printed thereon.